Offset change apparatus for traffic control systems



United States Patent [7 2] lnventors David Arlen;

John J. King, Jericho, N.Y. [21] App]. No. 671,737 [22] Filed Sept. 29,1967 [45] Patented Dec. 29, 1970 [73] Assignee Sperry Rand Corporation acorporation of Delaware [54] OFFSET CHANGE APPARATUS FOR TRAFFIC CONTROLSYSTEMS 15 Claims, 9 Drawing Figs.

[52] U.S. Cl. ..235/l50.24, 340/37, 340/40 [51] Int. Cl. ..G061' 15/48,008g 1/00 [50] Field of Search ..235/ 150.24; 340/35, 40, 41, 36

[56] References Cited UNITED STATES PATENTS 2,834,001 5/1958 Wilcox340/40X 2,288,601 7/1942 Barker 340/35 OF COMMAND AND GATES OFFSETSTORAGE REGiSTER 1 OFFSET oscooea 15 OFFSET SWITCHES 17 eucoozn OFFSETCOUNTER COUNTER OVERFLOW AND GATE FORWARD BACKWARD COUNTER 3,110,88111/1963 Paul 340/35 3,241,107 3/1966 Vivier 340/36 3,252,133 5/1966 Aueret a1. 340/35 3,252,134 5/1966 Auer et al.... 340/35 3,278,896 10/1966Auer et al..., 340/35 3,293,601 12/1966 Hendricks 340/35 3,305,8282/1967 Auer et a1. 340/40 3,307,146 2/1967 Auer et a1. 340/35 3,340,5029/1967 Huffman et a1. 340/35 Primary Examiner-Malcolm A. MorrisonAssistant Examiner-Felix D. Gruber A ttorney- S. C, Yeaton ABSTRACT:Offset change apparatus for vehicular traffic control systems forgradually and accurately changing the operative offset from an initialvalue to a new value by the shortest route utilizing a reversiblecounter to obtain the algebraic difference between the initial value andthe new desired offset value.

C5 GENERATOR CYCLE COUNTER CONTROL .12

ClRCUlTRV A SIGN GENERATOR PATENTEU 05029 I976 SHEET 3 OF 6 hwmmmo mqwJoQ24 Fwmwm O INVENTORS DAV/D ARLE/V JOHN J. K/IVG mum ATTORNEY PATENTEUnmzsmm 355L654 sum 5 or 6 A T T +A A v. SIGN FORWARD 0 BACKWARDDIRECTION OVERFLOW OVERFLOW DOWN BACKWARD FORWARD INVENTORS DA V/D ARLE/V JOHN J. K/NG BY ATTORNEY I OFFSET CHANGE APPARATUS FOR TRAFFICCONTROL SYSTEMS BACKGROUND OF THE INVENTION 1. Field of the inventionThe present invention relates to traffic control systems andparticularly to apparatus for gradually, accurately and smoothlychanging the offset at predetermined local traffic intersectioncontrollers without disturbing the flow of vehicular traffic.

2. Description of the Prior Art To fully appreciate the limitations ofthe prior artand to more readily understand the advantages of thepresent invention requires a brief description of the problem involved.

in many cities, efficient traffic flow can be obtained only throughintegrated control of a plurality of traffic signals located along atraffic artery. This permits employment of a progressive signaling.system wherein successive signals along the arteryare timed so thatvehicles travelling at a predetermined velocity encounter a green signalindication at each successive intersection, after having onceencountered a red signal indication along the artery. This requires thatthe local controllers for each of the succeeding signals be timed toinitiate a local cycle after, a predetennined interval from the time ofinitiation of the local cycle for the previously encountered signal.This interval, commonly known as local offset, may be obtained at eachlocal controller by' establishing a reference or background zerotime andhence a reference or background cycle duration for the entire system andrequiring the cycle timing means for each of the local controllers to betime-phased with respect to the system timing such that local zero timeat any controller bears a predetermined phase relationship to system orbackground zero time, even though the same cycle duration, i.e., thebackground cycle duration, may be demarcated at each controller. Thispredetermined phase relationship is independently selected at each localcontroller, permitting any predetermined offset to be obtained at anysuch location.

The speed of traffic ordinarily varies'with the amount of trafficcongestion, generally being relatively high when congestion is low anddecreasing substantially as congestion increases. This means that theoffsets for the various controllers must be adjustable so that theparticular offset values in effect at any time can readily be changed inaccordance with traffic congestion.

The offset times for the several controllers must usually be madeadjustable also in accordance with whether inbound or outbound trafficis to be favored at a given time. The offsets which must be establishedat the various'intersections to provide the proper progression for onedirection of traffic may be quite different from those which must be putinto effect to effeet a proper progression for traffic in the otherdirection. It is often necessary to favor one direction of traffic atone period of the day and to favor the opposite direction of traffic atother times since the relative trafiic loads may shift quite appreciablybetween different periods. Quite commonly, it is desirable to select oneset of offset values for the morning rush hour, a diflerent set for theevening rush, and a third set for other times when it is best to favorboth directions equally insofar as possible; these sets of values chosenin accordance with congestion. in any event, an integrated trafficsignal control system should provide a means by which a particular oneof a plurality of preset offset values can be selected at eachindividual controller location. For example, the system may be soorganized that one set of offset values is selected for the severalcontrollers in response to one kind of control signal received from thecentral office, and a second set of offset values in response to asecond different signal.

Changing of the local offsets at the local controllers from one value toanother when a new system offset has been established presents a designproblem, since it is undesirable to instantaneously shift from theprevious local offset value to the new local offset value. instantaneousshift in local offset may cause a significant portion of the local cycleto be skipped if the local cycle is required to start later in thebackground cycle, or may cause a portion of the local cycle to berepeated if the local cycle is required to start earlier in thebackground cycle. To avoid this situation, any change in offset at alocal controller must be accomplished gradually, over a period ofpossibly several background cycles if the change is drastic, so that notraffic phase is unduly lengthened or shortened. Hence, such change isaccomplished by a temporary but slight increase or decrease in localcycle duration.

Certain prior art systems for making such offset changes employelectromechanical components which tend to be unreliable in that suchcomponents are subject to deterioration in performance due toenvironmental conditions and excessive usage. 7

Certain other prior art systems, when effectuating a change from aprevious ofiset value to a newly commanded value, tend to overshoot thenew value by a substantial amount and thus are required to reverse thedirection of change to arrive at the new offset value. This proceduremay disrupt the smooth flow of traffic.

Other offset changing systems employ an offset controlling element and aplurality of remotely selectable elements, each preset to a particularoffset value. The offset controlling element is constrained to alignmentwith the selected element by means of a closed loop servomechanismarrangement. The effective offset at each controller is changed bychanging the selection from the plurality of elements. The offsetcontrolling element gradually realigns with the newly selected elementthus accomplishing the required change. Under certain conditions,servomechanism configurations are prone to instability which can resultin an oscillatory condition where the new off set value cannot bemaintained in a stable condition.

Still other systems, when changing offset, effectuate large changesduring the transitional cycles; thus confounding the efficientprogression of traffic. Such systems often employ numerous andcomplicated computations throughout the offset change procedure.

Aspreviously described, a reference zero time as well as a backgroundcycle duration must be established for an integrated traffic controlsystem. in the present apparatus, a sequence of. uniform pulses istransmitted from the central offree to a plurality of intersectioncontrollers. One distinctive pulse is transmitted for every group of I99uniform pulses. The distinctive pulse demarcates the reference zerotime, and the background cycle duration is determined'by the timeinterval between distinctive pulses. Thus every pulse representsone-half percent of the background cycle, the distinctive pulserepresenting 0 percent or the start of the background cycle. The l99thepulse following the distinctive pulse, thusly represents 99 /2 percentof the background cycle and the next occurring pulse, which is thedistinctive pulse, represents 100 hundred percent of the backgroundcycle as well as representing 0 percent of the next following backgroundcycle.

If, for example, an offset change from 10 percent to 90 percent ofbackground cycle is required, the transitional cycles can be slightlylengthened such that the transitional offset values will increase from10 percent until the required 90 percent is achieved. Thus theintersection controller must undergo a change of percent. if, however,the transitional cycles are shortened, the transitional offset valueswill decrease from 10 percent through 0 percent. Since 0 percent isequivalent to 100 percent, the values will further decrease untilpercent is attained. Thus, in the latter instance, the total offsetchange is 20 percent. It is apparent that by proper selection between ashorter or longer transitional cycle, the total change need never exceed50 percent of the background cycle.

The present invention contemplates subtracting the new offset value fromthe old offset value such that the algebraic difference is 50 percent orless by means of a reversible counter. In the previous example, the oldoffset value is 90 percent and the new offset value is 10 percent.Sincesubtracting 1.0 percent from 90 percent yields 80 percent, one ofthe factorsirnust be adjusted such that the difference will be 50percent or. less. Since percent is equivalent to 1 10 percent, thesubtraction-of l 10 percent from 90 percent yields an algebraicdifference of percent. 1

SUMMARY OF THE INVENTION the sign of the algebraic difference. Themagnitude of the difference controls the termination of the changeprocedure; The apparatus of the present invention gradually andaccurately changes theoperating offsct without requiring numerous andcomplicated numerical computations. Further, the offset change apparatusis utilized only during an offset change procedure when an offset changeis actually commanded. The

apparatus of the present invention does not require nor employelectromechanical components with their inherent difficulties explainedabove.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram in blockform of the offset change apparatus'of the present invention; FIG. 2 isa schematic wiring diagram of a portion of the control circuitry of FIG.1;

FIG. 3 is a schematic wiring diagram of another'portion of the controlcircuitry of FIG. l;

FIG. d is a schematic wiring diagram ofa portion of the forward-backwardcounter of FIG. 1;

FIG. 5 is a schematic wiring diagram of the sign generator of FlG. 1;

FIG. 6 is a schematic wiring diagram of the cycle counter of FIG; 1; 7

FIG. 7 is a schematic wiring diagram of the C5 generator of FIG. 1; and

FIGS. 8a and b are circular schematic drawings for explaining the offsetchange principle with respect to the apparatus of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT explanation of certain terms andwill not be repeated herein for the sake of brevity.

Referring now to FIG. 1, to provide an introductory synopsis the changeoffset operation is initiated by generating binary "ONE" signals on allfour offset command lines A, B, C, D,

' which extend between a zone control station and a local trafficintersection controller which houses the apparatus to be described. Theall ONES" pattern is presented at approximately the halfway point in thebackground cycle to AND gate 10 shown in FIG. 1 and AND gate Ill of FIG.2. The pattern lasts for a few cycle pulses, and then the binary signalsrepresenting the new offset command are presented on the offset commandlines A, B, C, D. The all ONES pattern generates the offset changecommand and arms the control circuitry 12 in a manner to be more fullydescribed. This maintain the nrevious or old offset si nal in the offsetstorage reoffset counter 18 which continues to generate the old offsetoverflow signal C5. When the offset "dou'n ter 1S overflows due to theall ONES pattern, the controlcircnitry 12 activates and reloads the oldoffset value into thelotifset.co unter 18. Then the tens quantized valueof this data: ist ransferred via AN D gate 20 to the forward-backwardcounterzl until the offset counter 18 overflows. The counter 21 is athree-stage double ranked counter which counts from 0 to 5 in 'theforward direction, and back to 0 inthe backward direction. An overflowsignal is generated when the counter 21 goes beyond count 5 in theforward direction or when it goes beyond count 0 in the backwarddirectiomThis overflow signal automatically causes the counter 21 tochange the direction of its count, i.e., from count forward. to countbackward and vice versa. The operation .of the counter 21 is such thatCounting occurs at one clock time, sensing a counter overflow at asecond clock time, storing the new count at a thirdjclock time andchanging counting direction at the fourth c'lock time. The clock timesare generated 'by conventional apparatus (not shown) within the localtraffic intersection controller. After the offset counter 18 overflows,control circuitry 12 then gates the new offset command into the offsetstorage register 13 through offset decoder 15, offset switches 1 6 andencoder 17 to the offset counter 18. The controlcircuitry 12 thenreverses the direction of the forward-backward counter, 21 and transfersthe tens quantized value of the, new data to the forwardbackward counter21. Thus, the new quantized datais subtracted from the contents of thecounter 21 which represented the old quantized data. The remainingcountin the forwardbackward counter 21 after this operation is the value ofdelta A and the counter direction is represented by the sign of delta A,i.e., or provided by the A sign generator 22. The control circuitry 12then senses the contents of the counter 21 to determine whether to startthe cycle counter 23, or to wait for the next background cycle. Thecycle counter 23 is a ninestage binary counter, which can count 256pulses. The counter 23 counts 1 percent pulses, where each pulse is aonehalf percent of cycle assuming a background cycle of 200 pulses. Theninth stage of the counter 23 is the overflow stage. The operation ofthe counter 23 is such that counting occurs at one clock time, overflowis sensed at a second clock time, reloading the counter at a third clocktime and clearing the ninth stage at the fourth clock time. The counter23 is preset to one of two values depending upon the sign of A. For -Asign, the counter 23 is preset to 36, which means the capability ofcounting 220 pulses or I 10 percent of the background cycle. For +Asign, the counter 23 is preset to 76, which means the capability ofcounting 180 pulses or percent of background cycle. The overflow of thecycle counter 23 is the C5 signal. The overflow signal C5 of the offsetcounter 18 and the overflow signal C5 of the cycle counter 23 are fed tothe C5 generator 25. The C5 generator 25. determines which of the twooverflow signals shall generate the offset signal C5. The CSsignal isthe operating offset signal for this background cycle in the localtraffic intersection controller; The C5 generator 25 is responsive tocontrol signals from the control circuitry 12 and the sign of A from theA sign generator 22 to determine the choice of overflow signal C5 or C5.An end of .offset change signal is generated in thecontrolcircuitry 12in the background cycle that the last offset change value occurs. Thissignal resets the armed offset change memory (not shown) which completesthe offset change procedure in a manner to be more fully described.

A detailed explanation of the present invention will now be provided byreferring initially to FIG; 2. The offset change control circuitry 12 isarmed by the all ONES pattern which enables AND gate 11. The AND gate 11sets the change offset C.O. flip-flop which prevents the offset storageregister 13 from receiving the new offset command at the next backgroundstart signal. At the next background start signal, a

resets the N flip-flop through OR gate 31. The controller generates fourclock times, i.e., w, x, y and z. Each clock time is 50 microsecondswide and there is a 50 microsecond dead time between two clock times. Atthe next x clock time, the AND gate 32 is enabled. The AND gate 32generates the clear signal. This signal resets the offset counter 18 toits initial condition, resets the percent count flip-flop (shown in FIG.3) through OR gate 33, resets flip-flop 1 (shown in FIG. 3) through ORgate 34. At this time the offset counter 18 (shown in FIG. 1) is readyto accept data from the'offset switches 16. At the next y clock time,the AND gate 36 (shown in FIG. 2) is enabledand generates s*** signal.This signal resets the forward-backward counter 21' to'its initial statethrough OR gates 40, 41, 42 (shown in FIG. 4), sets the directionflip-flop (shown in FIG. and sets the A start flip-flop (shown in FIG.2). At 66 milliseconds after the leading edge of the start pulse, aguard time signal is generated. This signal is over 100 millisecondswide. At the next y clock time, the AND gate 43 (FIG. 2) is enabled andgenerates the s? signal. This signal sets the percent count flip-flop(FIG. 3) and generates the s" signal through OR gate 44 (FIG. 2). The ssignal loads the data from the selected offset switch of the switches 16into the offset counter 18. Since the C.O. flip-flop is set, the oldoffset value is loaded into the offset counter 18.

At the next 1 percent pulse (2 clock time), the AND gate 45 (FIG. 3) isenabled and'its output is now used as the counting pulses by the offsetcounter 18. Thus the AND gate 45 presents z clock pulses to the offsetcounter 18 at the background cycle pulse rate until the offset counter18 overflows in a manner similar to that described in said Ser. No.453,072. At the time the offset counter 18 overflows, three pulses aregenerated. The first is the C5 signal and occurs at w clock time. Thesecond is the overflow x signal and occurs at x clock time. The third isthe overflow y signal and occurs at y clock time. The OR gate 47 (FIG.7) is enabled since the QC. flip-flop is off thereby providing an -O Csignal to the OR gate 47. The C5 signal therefore enables'the AND gate48 (FIG. 7) which enables the OR gate 49 and in turn enables the ANDgate 50, since the N flip-flop is off thereby providing an Esignal. TheAND'gate 50 generates the C5 pulse which at this time represents theoverflow signal associated with the old offset value. v

At this time the value of A and its sign are to be determined by thefollowingprocedure. Aty clock-time, the AND gate 51 (FIG. 2) is enabledthrough the overflow y signal and its output sets the N flip-flop andalso generates via OR gate 44 the s" signal which performs theoperations discussed above. The AND gate 12 (F IG. 3) is enabled by theN signal from the N flip-flop to' generate a train of z clock'pulses.These pulses will be used to transfer the units overflow from theofl'set counter 18 to the forward-backward counter 21. The numberof-overflows of the units counter portion of the offset counter 18represents the number of tens in the data since the counter 18 is adecade counter. Thus, the offset data in the counter 18 can be quantizedto tens, by monitoring the units counter If the data is generatedthrough four pulses, the next count A pulse will again set the x,flip-flop through the AND gate 55.

As shown in FIG. 5, at the next at clock time, the AND gate 66 sets theoverflow flip-flop via OR gate 67. At the next y clock time, the ANDgate 60 (FIG. 4) sets the x, flip-flop. At the next 2 clock time, theAND gate 68 (FIG. 5) is enabled, which enables OR gate 69. The OR gate69 output toggles the direction flip-flop. Since the direction flip-flopwas on before, the flip-flop is now toggled off, i.e., in the backwarddirection. If the data is greater than 5, the next count A pulse willenable the AND gate 56 (FIG. 4) which resets the .x flip-flop throughthe OR gate 40. At the same time, the overflow flip-flop (FIG. 5) isreset at w clock time through the OR gate 73. This operation willcontinue until all the data is transferred. Thus, the offset counter 18will overflow providing a C5 signal. At this time, the C5 signal enablesthe AND gate 48 (FIG. 7) which in turn enables the OR'gate 49. However,no C5 signal is generated for this offset counter overflow since the Nflip-flop is on and the AND gate is therefore disabled.

The new offset data is now loaded into the offset counter 18, andsubtracted from the old ofi'set data in the forwardbackward counter 21.At the same w clock time, as the C5 signal, the AND gate 80 (FIG. 2) isenabled and generates an L* signal. This signal allows the new offsetcommand to be inserted into the offset storage register 13 and resetsthe A start flip-flop through the OR gate 30. At the next y clock time,the overflow y, signal enables the AND gate 81 which generates the L**"signal. The l..*** signal sets the QC. flip-flop, ahd loads the newoffset data into the offset counter 18 through the s** signal generatedby OR gate 44. The I.*** signal also enables the OR gate 69 (FIG. 5)which toggles the direction flip-flop thus changing the countingdirection in the forward, backward counter 21. The L".**' signal alsoresets the overflow flip-flop through the OR gate 73 (FIG. 5). This isto prevent a double toggle of the direction flip-flop in case of acounter overflow in the previous w clock time. The O.C. flipflop (FIG.2) is the change offset memory.

At the next 2 clock time, the new data is transferred to theforward-backward counter 21. Thus, the operation as described in theprevious paragraph above is repeated. At the offset counter overflowcaused by the transferring of the new offset value, the AND. gate 82(FIG. 2) is enabled and generates the D*** signal which gates the stateof the direction flip-flop (FIG. 5) into the A sign flip-flop via ANDgates 83 and 84. At the next x clock time, the AND gate 85 (FIG. 2) isenabled which generates the D" signal. The D signal preloads the cyclecounter 23 (FIG. 6) to the proper point through OR gate 86 and eitherAND gate 87 or 88. The

' D" signal also sets the V(w) flip-flop (FIG. 3). At the next y clocktime, the AND gate 90 (FIG. 2) is enabled which generates the D" signal.The D* signal resets the N flip-flop through OR gate 31, resets thedirection flip-flop (FIG. 5) and overflow. Then at the same time as ANDgate 12 is enabled,

the AND gate 52 (FIG. 4), which is included in the AND gate 20 (FIG. 1is enabled to accept the units counter overflow.

The output of gate 52 enables OR gate 53 which generates the count Asignal that is counted in the forward-backward counter 21. As shown inFIG. 4, the'old offset data will now be counted into theforward-backward counter 21. The first count A pulse enables the ANDgate 55, since the x, flip-flop is off and provides an i signal. The ANDgate 55 sets the x, flip-flop and partially enables the AND gate 58.Since the counter 21 is in the forward direction, the AND gate 58 isdisabled. At y clock time, the AND gate sets the x, flip-flop to providean x, signal. The second count A pulse enables the AND gate 56, since1:, flip-flop is on. The AND gate 56 enables the AND gate 59 and the ORgate'40. The OR gate 40 output resets the x, flip-flop. The AND gate 59enables OR gate 54 since the counter is in the forward direction. The ORgate 54 enables the AND gate 61 since the y,

aligned to reduce the value therein to zero.

resets the overflow flip-flop through OR gate 73. The overflow flip-flopis reset in order to prevent a toggling of the direction flip-flop. Atthis time the value of A and the sign of A have been generated. Thevalue of A is stored in the forwardbackward counter 21 and the sign isin the A sign flip-flop (FIG. 5). Also, the forward-backward counter 21has been Now the system determines if A is zero. A A value of means thatthe difference in offset between the old and the new is less than l0percent. If A is zero, the system will jump immediately to the newoffset, otherwise it will proceed with the offset change operation. If Aequals zero at D" time, the contents of the forward-backward counter 21is zero. Thus, AND gate 91 (FIG. 3) is enabled which enables AND gate92. The AND gate 92 sets the GE. flip'flop through OR gate 93, resetsflip-flop 01 through OR gate'34 and resets flip-flop 02 through OR gate35. The normal procedure in offset change flip-flop is off 5 operationis blocked by AND gate 94. The operation then waits for the nextbackground start at which time the new offset is loaded into and countedby the offset counter 18 and the operation described above with respectto the comparable background start is repeated. Since A is zero, the Asign flipflop (FIG. is in a +A state. Also,because A is zero, theauxiliary counter flip-flop (FIG. 6) is off. Thus OR gate 95 (FIG. 7) isenabled,'which enables AND gate 96. The AND'gate 96 in turns enables theOR gate 47. Thus, when the new offset C5 signal is generated, it willenable AND gate 48 which enables the OR gate 49 and thus the AND gate50. The AND gate 50 generates the C5 signal. The C5 signal is theoperating offset signal for this background cycle in the local trafficintersection controller. This signalenables the AND gate 97 (FIG. 3).The AND gate 97 generates the end of offset change signal, which resetsthe QC. flip-flop (FIG. 2) thus resetting the offset change memory. Atthe next y clock time, the AND gate 98 (FIG. 3) resets the GE.flip-flop. Thus the offset change circuitry is completely off. In thenext background cycle, the new offset value is directly generated by theoffset counter 18.

The operation of the ZERO OFFSET circuit will be described with respectto FIG. 3. For'this condition, at D* time, the forward-backwardcounter21 contains a count of one. The AND gate 92 is blocked and theAND gate 94 is enabled. The AND gate 94 generates the V(w)w signal,which reduces the count in the forward-backward counter 21 by onethrough OR gate 53 (FIG. 4). The V(w)w signal also sets the LC.flip-flop. The AND gate 99 is enabled if the new offset value is greaterthan the old offset value, through AND gate 101 (FIG. 5). The'joutput ofthis gate sets the flip-flop 1. At an x clock time later, theforward-backward counter- 21 overflows, and enables AND gate 100 throughANDgate 101 (FIG. 5). The'AND gate 100 (FIG. 3) sets the CE. flip-flopthrough OR gate 93. When the C.E. flip-flop is set, it indicates thatthe change offset operation will be completed in the next backgroundcycle. At the same time the AND gate 102 resets the V(w) flip-flopthrough the OR gate 103, sets the flip-flop 3 and sets the auxiliarycounter flip-flop (FIG. 6). At the same time if the sign of A isnegative, the AND gate 104 is enabled (FIG. 3). This gate generates thereset and clear ofiset counter signal which prevents the C5 signal fromgenerating a C5 signal in the same background cycle as'the C.E.flip-flop is turned on. At the same time AND gate'105 is enabled, whichgenerates the CF signal. The CF signal sets the flip-flop 2 and resetsthe auxiliary counter flip-flop FIG. 6) through OR gate 44. At the nextw clock time, AND gate 106 (FIG. 3) resets the IC flip-flopand the laststage of the cycle generator 23 (FIG. 6). The circuitry now waits forthe next background start.

The start pulse enables AND gate 108 (FIG. 3) which sets the Sflip-flop, and resets the A start and N flip-flops. Thus, the new offsetvalue is loaded and counted in the offset counter 18. The AND gate 108generates the CSF signal which generates the C5 signal through OR gate49 and AND gate 50 (FIG. 7). The C5 signal is the operating offsetsignal, for this background cycle in the local traffic intersectioncontroller.

Thus the offset counter 18 is counting, and a zero offset is generated.The C5 signal enables AND gate 97 which generates the end of offsetchange signal. This signal clears the OC and CE flip-flops in a mannerexplained above. As. shown in FIG. 7, when the offset counter 18overflows, the C5 signal generates the C5 signal through the OR gate 47,AND gate 48,

OR gate 49 and AND gate 50. Thus, during the same.

background cycle, two operating offset signals are generated.

When the difference in offset is greater than percent, the

AND gate 91 (FIG. 3) is disabled since the forward-backward counting thenew offset value as explained above. When the cycle counter 23 overflowsat w clock time, the AND gate Ill (FIG. 6) generates the C5 signal-TheC5" signal resets the auxiliary count flip-flop through the OR gate 44.Forthe conditions of +A sign operation, the C5 signal is chosen from thecounter overflow occurring last (CS' or C5"). The C5" signal is chosenas shown in FIG. 7 through OR gate 112, AND gate 113, OR gate 49 andANDgate 50. The C5 signal is chosen through OR gate 95, AND gate 96, ORgate 47, AND gate 48, OR gate 49 and AND gate 50. For the condition of Asign operation, the C5 signal is chosen from the counter overflowoccurring first (CS' or C5"). The gating is the same as previouslyexplained. At the next xclock time, as shown in FIG. 6, the cyclecounter 23 is preloaded through OR gate 86 and either AND gate 87 or 88.The C5 signal generates the end of offset change signal through AND gate97 (FIG. 3). This signal clears the OC flip-flop (FIG. 2) and CEflip-flop (FIG. 3). At the next z clock time,the AND gate 115 (FIG. 6)resets the cycle counter overflow stage. Thus the offset changecircuitry is reset. If the counter contains a count greater than 1, thesteps are repeated with the C5" signal again generating the V(w)w signalthrough OR gate 116 and AND gate 94 (FIG. 3). The operation is continueduntil the count in the forward-backward counter 21 is reduced to l andultimately until the offset change circuitry is reset as explainedabove.

' As explained above, once the value and sign of A are determined, aninternal cycle clock is started. The internal clock counts up to eitherpercent of the background cycle (for +A) or I 10 percent (for A). Theinternal cycle clock is started at the point when the offset counter 18containing the old offset value overflows. The term old offset" refersto the operating offset before the offset change procedure explainedabove. Conversely, the new offset refers to the operating offset afteran offset change procedure. When the cycle clock overflows providing aC5" signal, it is used as the first offset change point C5 for thatbackground cycle. The value of A is then reduced by one, and the cycleclock is reset and is started counting again. This operation continuesuntil the value of A is zero. At each background cycle during the offsetchange operation, the offset counter 18 generates the new offset valueC5. At the background cycle that A equals zero, the change offset pointC5 is-chosen from either the cycle clock overflow signal or the offsetcounter overflow signal. The choice is a function of the direction inwhich theoffset change is being made, i.e., the sign of A. The conceptof two clocks simultaneously running and choosing one overflow (at A=0), removes any anomalies that might otherwise exist. Further, theoffset changes are true 10 percent incremental changes, not 10 percentof the quantized values.

As an example of. this method will be described referring to FIG. 8.Assume that an offset change from 22 percent to 67 percent is requiredas shown in FIG. 8a. The operation would be to calculate the magnitudeof A A 4] the sign of A (sign A). At old offset point, i.e., 22 percentin the background cycle, the internal cycle clock is set to count I10percent, starts counting and the value of A is decreased to 3. In thenext background cycle, the cycle clock overflows at 32 percent.

Thus, the first offset change value is 32 percent. A is decreased to 2,and the cycle clock resets to percent and starts counting again. In thesecond background cycle, the offset change value is 42 percent. In thethird background cycle, the

offset change value is 52 percent and A is decreased to 0. In

the fourth background cycle, the circuitry would choose as the offsetvalue theoverflow, i.e., C5 or C5" whichever occursl first. In otherwords, at this background cycle the amount of offset change needed toobtainthe new offset value is l5 percent (67 percent-52 percent), Thusby choosing the cycle clock overflow, the system stays within the 10percent step requirement. Then in the fourth background cycle, theoffset change value is -62 percent. In the next background cycle, the

circuitry'generates the new offset value (67 percent).

As a second example, as shown in FIG. 8b, assume an offset change in theopposite direction'from 62 percent to 27 percent. The value of A isagain 4, but the sign is +A. Atthe old offset point (62 percent), thecycleclockis set to count 90 percent of background cycle. The value of Ais decreased to 3, and the counter starts counting. in the firstbackground cycle, the offset change value is 52 percent and A decreasedto 2. in the second background cycle,- the offset change value is 42percent and A-decreased to 1. In the third background cycle, the offsetchange value is 32 percent and A decreased to 0. In the fourthbackground cycle, the system selects as the offset value the overflow Cor C5" which occurs last. At this background cycle, the amount ofoffset'change needed to obtain the new offset value is 5 percent. Thusby choosing the.

offset counter overflow C5, the system will pass over the cycle clockoverflow value. Then, the offset value for this circuit is activated.The gate description of this circuit was.

discussed previously. This condition exists for changes in offset ofless than percent, where the old offset is less than 10 percent and thenew offset is greater than 90 percent. For this condition the value of Aequals 1, and sign is +A. When A is decreased to 0, the circuitry willattempt to choose between the two overflows. Since A is decreased to 0in the same background cycle as the operation began, the offset counterwill not begin counting the new offset until the next background cycle.Thus, inthe initial background cycle, only the cycle clock overflow C5"will be generated. Hence, the circuitry chooses the cycle clockoverflow. For a change offset of 2 percent to 98 percent, the firstbackground cycle would give the offset values, 2 percent and 92 percent.Thus, passing 1 over the new offset value. This operation is modified bythe zero offset circuit. The circuit stops the counting of the cycleclock, and generates a zero offset signal C5 in the next backgroundcycle. Thus in the first background cycle it would have two offsetvalues, i.e., 0 percent offset and the new offset.

While the invention'has been described in its preferred embodiment, itis to be understood that the words which have been used are words ofdescription rather than limitation and that changes within the purviewof the appended claims may background cycle from a first offset value toa second offset value upon initiation of a command signal comprising,

a. control means adapted to be enabled by said command signal to changethe offset valuefrorn said first to said second value;

b. offset timing means sequentially responsive to signals representativeof said first and second offset values for generating first and secondoffset signals respectively in accordance with first and second offsetcycles;

0. computing means coupled to said control means and said offset timingmeans for obtaining the algebraic difference between said first andsecond offset values when said control means is enabled such that saidalgebraic difference represents an offset change not in excess of fiftypercent of said background cycle;

d. cycle timing means responsive to said control means and saidcomputing means for generating successive transitional offset signalswhen said control means is enabled for initiating successivetransitional offset cycles selectively shorter or longer than saidbackground cycle in accordance with the sign of said algebraicdifference; and

e. selection means responsive to said offset timing means and said cycletiming means for selecting between said second offset signal and saidtransitional offset signal for initiating the operational cycles of saidcontroller such that said operational cycles change gradually towardssaid second offset cycle.

2. In apparatus of the character recited in claim 1 and furtherincluding:

diminishing means coupled to said computing means for graduallydiminishing the absolute value of said algebraic difference; and

terminational means responsive to the zero value of said algebraicdifference for disabling said control means.

3. ln apparatus of the character recited in claim 1 wherein said offsettiming means includes a two-stage decimal counter having a units orderstage and a tens order stage where said second offset signal is derivedfrom an overflow signal from said tens order stage.

4. ln apparatus of the character recited in claim 1 wherein saidcomputing means comprises:

forward-backward counter means having a full count representing 50percent of said background cycle and adapted to count forward uponattaining the count of zero and adapted to count backward upon attainingsaid full count;

means for sequentially counting said first offset value and said secondoffset value into said counter means;

means for reversing the direction of count between said counting of saidfirst and second offset values; and

means for storing said direction of count after counting said secondoffset value.

5. In apparatus of the character recited in claim 4 wherein said cycletiming means comprises additional counter means adapted to count atransitional cycle time duration selectively shorter or longer than saidbackground cycle, said selection being dependent on said storeddirection of count.

6. In apparatus of the character recited in claim 5 wherein said shortertime duration is selected if said stored direction of count is backwardand wherein said longer time duration is selected if said storeddirection of count is forward.

7. in apparatus of the character recited in claim 5 wherein said shortertime duration is percent of said background cycle duration and whereinsaid longer time duration is l 10 percent of said background cycleduration.

8. In apparatus of the character recited in claim 2 wherein saiddiminishing means diminishes theabsolute value of said algebraicdifference during each transitional cycle by an 9. in apparatus of thecharacter recited in claim 1 and further including quantizing meansresponsive to said enabled control means for numerically rounding saidfirst and second offset values to the nearest higher power of 10 and fordividing said rounded values by 10, and wherein said computing meansresponsive to said enabled control meansalgebraically subtracts saidquantized second offset value from said quantized first offset valuesuch that the algebraic difference in absolute value is not in excess of5.

10. In apparatus of the character recited in claim 9 wherein saidquantizing means and said offset timing means include a two-stagedecimal counter having a units order stage and a tens order stagewherein said quantized offset values are derived from the overflowsignal from said units order stage and said second offset signal isderived from the overflow signal from said tens order stage.

11. In apparatus of the character recited in claim 9 wherein saidcomputing means comprises:

a modulo six forward-backward counter adapted to count forward uponattaining the count of zero and adapted to count backward upon obtainingthe count of five;

means for sequentially counting said quantized first offset value andsaid quantized second offset value into said counter;

means for reversing the direction of count between said counting of saidquantized first and second offset values; and

means for storing said direction of count after counting said quantizedsecond offset value.

12. In apparatus of the character recited in claim 11 wherein said cycletiming means comprises still another counter adapted to count atransitional cycle time duration background cycle duration and whereinsaid long time duration is l 10 percent of said background cycleduration.

15. In apparatus of the character recited in claim 9 wherein saiddiminishing means diminishes the absolute value of said algebraicdifference by unity each transitional cycle until said absolute value isreduced to zero.

